1. Field of the Invention
The present invention relates to a processor, and more particularly to a system processor including a memory and a cache memory therein.
2. Description of the Prior Art
Referring to FIG. 5, there is illustrated a view of a system arrangement exemplarily illustrating a prior art processor. In the figure, designated at 1 is an instruction fetch section as instruction read means for reading an instruction, 2 is an instruction fetch program counter for indicating the address of any instruction read in by the instruction fetch part 1, 3 is an instruction break point register as an instruction break pointer, 4 is a comparator for comparing the instruction fetch program counter 2 with the instruction break point register 3, 5 is a decoder section as instruction decoder means for decoding any instruction, 6 is a decode program counter for indicating the address of any instruction being decoded in the decoder part 5, 7 is a 1 bit register for indicating a result of comparison between the instruction fetch program counter 2 and the instruction break point register 3 concerning any instruction being decoded in the decoder section 5, 8 is an operand fetch section as data access means for accessing data, 9 is an operand fetch program counter for indicating the address of any instruction using data accessed by the operand fetch part 8, 10 is a 1 bit register for indicating a result of comparison between instructions at the instruction fetch program counter 2 and the instruction break point register 3, each instruction employing data accessed by the operand fetch section 8, 11 is an operand register as data address designation means for indicating the address of the data accessed by the operand fetch section 8, 12 is a data break point register as a data break pointer, 13 is a comparator for comparing the contents in the data break point register 12 and in the operand register 11, 14 is an execution section for executing operations and the like, 15 is a program counter for indicating the address of any instruction in running, 16 is a 1 bit register for indicating a result of comparison between instructions in running at the instruction fetch program counter 2 and the instruction break point register 3, 17 is a 1 bit register for indicating a result of comparison between instructions in running at the data break point register 12 and the operand register 11, 18 is a memory for storing instructions and data, 19 is a cache memory for storing part of contents in the memory 18, 26 is a memory controller for controlling the cache memory 19, 27 is an access completion signal issued from the memory controller 26 to a microprocessor 21, and 28 is a hit signal issued from the cache memory 19 to the memory controller 26. Herein, the memory 18 and the cache memory 19 are external to the microprocessor 21 in the present example.
Operation of the prior art processor is as follows.
Referring again to FIG. 5, the microprocessor 21 transmits and receives information to and from the memory 18 and other peripheral devices (not shown) for processing of the same. An access speed to the memory 18 is typically lower than a processing speed of the microprocessor 21, and hence the memory controller 26 generally stores part of contents of the memory 18 in the higher access speed cache memory 19.
Debugging is frequently required for development of programs and systems by interrupting the running of a user program in the course of programming and by an access to particular data. Accordingly, the prior art processor includes the instruction break point register 3 as an instruction break pointer and the data break point register 12 as a data break pointer. To the instruction break point register 3 an address in the user program desired to be interrupted is set, and to the data break point register 12 an address in the user program desired to be interrupted as being read or written is set.
Execution of a program in the prior art processor is as follows. An address in the program is set to the instruction fetch program counter 2 in the instruction fetch section 1 of the microprocessor 21. The instruction feth section 1 informs the bus interface 20 of the address, which interface 20 in turn instructs the memory controller 26 to read out the address. The memory controller 26 judges whether or not the address is existent in the cache memory 19. More specifically, once the address is supplied to the cache memory 19, and the cache memory 19 stores therein information concerning the foregoing address, it issues a hit signal 28, and otherwise does not issue such a signal. Provided the foregoing address is existent in the cache memory 19, the memory controller 26 does not read the address from the memory 18 but reads an instruction in the cache memory 19. Thereupon, the access completion signal 27 is issued in the shortest time. Contrarily, provided there is not existent the associated address in the cache memory 19, the memory controller 26 reads the associated address from the memory 18 and updates the contents in the cache memory 19 at need. Thereupon, the access completion signal 27 is issued not in the shortest time but after a necessary time. Further, the comparator 4 compares the instruction fetch program counter 2 with the instruction break point register 3. A count value by the instruction fetch program counter 2 in the instruction fetch section 1 is sent to the decode program counter 6 in the decoder section 5, and a result of the comparison by the comparator 4 sent to the 1 bit register 7, and further the instruction read by the memory controller 26 sent to the decode section 5 through the bus interface 20.
The decoder section 5 decodes the instruction. The count value of the decode program counter 6 in the decoder section 5 is sent to the operand fetch counter 9, the value in the 1 bit register 7 sent to the 1 bit register 10, and the instruction information decoded by the decode section 5 is sent to the operand fetch section 8. In this instruction information, data used by the instruction or the address at which a result of the instruction is stored is set to the operand register 11.
The operand fetch section 8 informs the bus interface 20 of the address of the data used by the instruction, and the bus interface 20 instructs the memory controller 26 to read out the associated address. The memory controller 26 judges whether or not the associated address is existent in the cache memory 19. More specifically, with the address being sent to the cache memory 19, if the cache memory 19 holds therein information concerning the address, it issues a hit signal 28 while unless it holds the same, it issues no hit signal 28. Provided the associated address is existent in the cache memory 19, the memory controller 26 does not read that address from the memory 18, but reads out an instruction in the cache memory 19. Thereupon, the access completion signal 27 is issued in the shortest time. Unless the associated address is existent in the cache memory 19, the memory controller 26 reads out the associated address from the memory 18 and updates the contents in the cache memory 19 at need. In this case, the access completion signal 27 is issued not in the shortest time but after the elapse of a required time. Further, the comparator 13 compares the operand register 11 with the data break point register 12. Thereafter, the operand fetch program counter 9 in the operand fetch section 8 is fed to the program counter 15 in the execution section 14, the 1 bit register 10 fed to the 1 bit register 16, a result of comparison in the comparator 13 fed to the 1 bit register 17, and instruction information decoded by the decoder section 5 and the data read out by the memory controller 26 are fed to the execution section 14 through the bus interface 20.
If the 1 bit register 16 and the 1 bit register 17 are not zero, then the execution section 14 executes the instruction using the instruction information decoded by the decoder section 5 and the data read out through the bus interface 20. The operand fetch section 8 informs the bus interface 20 of an address at which an instruction result is stored, which interface 20 in turn instructs the memory controller 26 to write the instruction result at a location of the associated address. The memory controller 26 updates the contents in the cache memory 19 and in the memory 18, at need.
The instruction fetch program counter 2 is successively incremented as the program is sequentially executed or a new value is set thereto in conformity with the instruction. The instruction fetch section 1, decoder section 5, operand fetch section 8, execution section 14, and bus interface 20 process the program concurrently or sequentially.
Provided the 1 bit register 16 or 1 bit register 17 in the execution section 14 is 0, the execution section 14 interrupts its execution of the instruction and sets an address of a debugging routine to the instruction fetch program counter 2. Information concerning the decoder section 5, operand fetch section 8, and execution section 14 is ignored at this time. A user performs debugging using a debugging routine. It is possible here to know that the interruption of the execution of the instruction originates from the data or the instruction with reference to the 1 bit register 17 and the 1 bit register 16.
There are included as the cache memory 19 those of storing only instructions, those of storing instructions and data without distinguishing those signals, and those of storing separately instructions and data. There are herein supposed those of storing instructions and data without distinguishing those signals and those of storing separately instructions and data. However, provided those of storing only instructions are supposed as the cache memory 19, the memory controller 26 surely accesses the memory 18 but does not access the cache memory 19 when there are performed readout and write operations in the operand fetch section 8.
With the arrangement described above, the prior art processors however suffer from a difficulty: Although the contents in the cache memory 19 are successively updated in conforming with the types of the cache memory 19, there is no means for simply knowing whether instructions and data to be debugged are existent in the cache memory 19 or existent in the memory 18. It is therefore difficult to adjust the effect of the cache memory 19 in detail upon any program and system being debugged. More specifically, the cache memory 19 stores therein instructions or data to which many accesses are taken and of which frequent use is made as well as stores instructions or data to which less accesses are taken, but storage of frequently used instructions and data in the cache memory 19 and in turn locking of the same rather cause those instructions or data to be accessed in a short time and hence access time to be shortened as a whole. It is however impossible in the prior art to know whether any read instruction or data is existent in the cache memory 19 or in the memory 18. It is therefore impossible to know the number of times of accesses to any specific instruction or data from the cache memory 19. This makes it impossible to lock frequently used instructions or data in the cache memory 19. The locking herein means that when the cache memory 19 is fully filled with information, the associated instruction or data is stored therein over a long time and instructions or data other than the associated one are driven out.